Integrated circuits are electronic circuits which normally include a very large number of semiconductor elements, such as transistors and diodes, as well as other electronic components, in highly compact form on a silicon wafer. The basic principle underlying integrated circuits is that instead of building an electronic circuit out of discrete components such as transistors, diodes, resistors and capacitors, the entire circuit is fabricated on the same piece of silicon in the form of a number of superimposed layers of conducting, insulating and transistor forming materials. By arranging predetermined geometric shapes in each of these layers, a circuit having a required function is realized.
The process by which an integrated circuit is fabricated is long and complex and basically includes the following steps:
1. A polished silicon wafer is exposed to an appropriate material in a high temperature furnace in order to "grow" a uniform layer of the material on its surface. PA1 2. After the wafer is cooled, it is coated with a thin film of resist material, which is dried and baked. PA1 3. At the same time, a mask for the appropriate layer is created, which defines the precise pattern required on the silicon surface. PA1 4. This mask is brought firmly into proximity with the coated wafer and exposed to intense ionizing radiation such as ultraviolet light or low-energy x-rays. In areas wherein the mask is transparent to such radiation, the ionizing radiation passes into the resist and breaks down its molecular structure. The portions of the resist that are covered by opaque portions of the mask are not affected. PA1 5. The resist is then developed by immersing the silicon wafer in a solvent which dissolves the resist only at the locations which were exposed to the ionizing radiation. PA1 6. The wafer is then exposed to an appropriate etching material which is effective to remove the material grown previously thereon (Step 1), except where the material is covered by resist, thus defining a desired pattern of the grown material. PA1 7. The remaining resist material is then removed. PA1 a. A large number of printed circuit boards are required, resulting in an expensive product, relatively long assembly time, relative difficulty in maintenance and troubleshooting and large size. PA1 b. Lower electrical power efficiency is realized. As a result, relatively larger power sources are required and heavier and larger products result.
The above process is repeated for each of the layers of material forming the integrated circuit. In most integrated circuit technology one or more layers of metal are employed for internal connections on the integrated circuit. These metal layers are usually formed last.
As can be readily appreciated, the above process requires sophisticated machinery and custom masks which must be specially set up for each specific type of custom integrated circuit to be fabricated. For the process to be at all economical, extremely large quantities of integrated circuits must be produced for a given set up. Since there exist applications wherein the quantities desired of a specific circuit are not extremely large, techniques have been developed for producing integrated circuits known as gate arrays. In these gate arrays, a large amount of transistors and other components are produced by the above-described mass production techniques. Specific interconnections therebetween suitable for a specific circuit are then formed on the chip by etching a suitable metal layer thereon. There exist advanced gate-arrays wherein two or more layers of custom metal interconnections may be custom etched.
Despite the use of sophisticated computer aided design and semi-custom devices, the widespread use of dedicated non-standard integrated circuits is still limited because of the high costs and long lead time involved in their fabrication. Many users of integrated circuits still make extensive use of standard, "off the shelf" available small scale and medium scale integrated circuits.
Electronic circuits manufactured by combining a large number of such standard integrated circuits have a number of disadvantages:
There are known integrated circuits such as EPROMS and PALS (programmable array logic) which are programmed by fusing which is accomplished electrically via the integrated circuit's input/output pins, requiring elaborate extra fusing circuitry for this purpose.
There are also known techniques for increasing yield of integrated circuits by excising inoperative portions thereof by fusing. This is normally done on wafers including a multiplicity of integrated circuits.
It is also known to produce gate arrays which are laser programmable. Such devices are described in a publication of Laserpath, Inc. of Sunnyvale, Calif. 94086 USA entitled "One Day Prototype Laser Programmed Arrays" dated Feb. 26, 1986.
Dual metal layer integrated circuit technology has been developed in recent years to enable automatic computer software controlled generation of integrated circuit layouts, commonly known as routing. In the early years of integrated circuit development, routing was done by hand. Due to the increased complexity and density of contemporary integrated circuits, manual routing is no longer possible.
Dual metal layer technology provides two independent routing layers extending in respective perpendicular directions, commonly termed North-South and East-West. Changes in direction are provided by vias which interconnect the two layers, the vias typically being defined by an opening in the insulating layer between the two metal layers, being filled by metal from one of the two layers. A simple dual metal layout wherein vias are positioned at the locations of the desired direction changes is shown in FIG. 1A, wherein the horizontal strips are typically a metal I layer, indicated as M1, the vertical strips are typically a metal II layer, indicated as M2, and the vias interconnecting the two layers are labeled. The metal II layer overlies the metal I layer.
In order to permit rapid customization of dual metal type integrated circuits, it is desired that such customization be solely produced by fuse disconnection rather than by applying metal across a gap. Accordingly, configurations such as that shown in FIG. 1B were developed to combine the advantages of automatic routing with those of rapid customization, such that customization can be carried out by an automatic routing technique. In the configuration of FIG. 1B the East-West strips are indicated to be metal I while the North-South strips are indicated to be metal II and a via connecting the metal I and metal II layers is disposed adjacent each crossing of the respective metal I and metal II strips. The via underlies the metal II strip and is joined to the metal I strip by means of a branch having a fuse formed thereon. Fuses are also provided along the metal II strips between adjacent vias and along the metal I strips between adjacent branches.
Customization of the blank shown in FIG. 1B takes place by traveling along the metal I strips and fusing all fuses on the branches which are not used. If a direction change is desired, a branch is used to establish a connection to the metal II layer. When traveling along the metal II strips, if the desired direction of the strip is, for example, South, the fuses lying to the North are fused or vice versa. FIG. 1C illustrates the equivalent circuit to that shown in FIG. 1A embodied in the structure of FIG. 1B, where /'s over the fuse indicate fused fuses.
U.S. Pat. No. 4,197,555 to Uehara describes a structure in which a relatively long strip of M1 is used. Although this structure is adequate for PAL configuration applications, it is relatively unsuitable for gate array applications, particularly if an automatic place-and-route program is used. Also, the length of the M1 strip acts to increase the line capacitance.
The following patents and copending applications of the Applicant disclose apparatus and techniques, particularly with respect to fusing, which may be useful in putting the present invention into practice: U.S. Pat. No. 4,924,287; U.S. Pat. No. 5,111,273; U.S. Pat. No. 4,875,971, USSN 368,161 filed 16 June, 1989. The disclosures thereof are hereby incorporated by reference.